1. Field of the Invention
The present invention relates to a digital signal noise shaping requantizing circuit, and in particular to a noise shaping requantizing circuit which utilizes a multi-stage noise shaping technique.
2. Description of the Related Art
In recent years, in accompaniment with advances that have been made is digital signal processing technology, digital signal processing has come increasingly into use in fields where analog signal processing was previously utilized. Requirements have therefore arisen for improved performance of digital-to-analog converters, and for these to be produced at lower cost. Noise shaping quantization is a technique that has been developed to meet these requirements. An example of a noise shaping quantizer circuit is described in Japanese Patent Laid-open No. 63-209334, with the title "Quantizer Using Noise Shaping". That circuit uses multi-stage noise shaping, i.e. whereby a quantization error generated in a first delta-sigma quantizer which executes noise shaping of an input signal is inputted to a second delta-sigma quantizer, whose output signal is differentiated and added to the output from the first delta-sigma quantizer. Such a circuit enables high-order noise shaping to be achieved without the danger of oscillation occurring in the circuit. However it has the disadvantage of requiring a higher degree of quantization resolution of the output signal, by comparison with a quantization circuit which provides only low-order noise shaping (e.g. a circuit consisting of only one single-integration delta-sigma quantizer). For that reason, new types of quantization circuit have been proposed, for example as described in the I.E.E.E. Journal of Solid State Circuits, August 1989, Vol. 24 No. 4, whereby it becomes unnecessary to increase the degree of quantization resolution of the output from the circuit (i.e. by comparison with a circuit which provides only low-order noise shaping), in order to achieve high-order noise shaping operation.
That circuit is shown in FIG. 18, implemented as a noise shaping requantizing circuit, i.e. a circuit which converts an input digital signal having a high value of quantization resolution to an output digital signal having a lower value of quantization resolution and a higher sampling frequency than that of the input signal. In FIG. 18, the input digital signal is designated as X, and the output digital signal as Y. A digital integrator 102 is formed of a delay element 127 (providing a unit delay, represented by the delay operator z.sup.-1, that is equal to the sampling period of the input digital signal) and an adder 126. That integrator 102, in conjunction with a local quantizer 103, an adder 128, a delay element 4, and a subtractor 101, forms a main loop 100 which constitutes a first-order delta-sigma quantizer, sometimes referred to as a single-integration delta-sigma quantizer. An adder 120 and a delay element 121 form an integrator 108, while an adder 122 and a delay element 123 form an integrator 110. A subtractor 107 and a subtractor 109, a local quantizer 111, the integrators 108 and 110, and a delay element 112 form a sub-loop 106 which constitutes a second-order delta-sigma quantizer, sometimes referred to a single-integration delta-sigma quantizer. In the sub-loop 106, the subtractor 2 derives the difference between the input and output signals of the local quantizer 103. In addition, the output signal produced from the integrator 108 is multiplied by a predetermined coefficient "a" by a multiplier 130, and the result is added to the input signal of the local quantizer 103 by the adder 128. It will be assumed that the input signal X is a 16-bit digital signal, and that the quantization that is executed by the local quantizers 103 and 111 is expressed by the appended Tables 1 and 2, respectively. The output values are normalized to 16384.
Designating the quantization error of the local quantizer 103 as Vq1, and the quantization error of the local quantizer 111 as Vq2, the input signal X and the output signal Q1 from the main loop 100 have the following relationship: EQU Q1=X+(1-z.sup.-1).multidot.Vq1 (1)
The input signal X' and the output signal Q2 of the sub-loop 106 are related as follows: EQU Q2=X'+(1-z.sup.-1).sup.2 .multidot.Vq2 (1)
Since the output produced from the subtractor 2 is the difference between the input and output signal values of the local quantizer 103, the following is true: EQU X'=-Vq1 (3)
The output Q2 from the sub-loop 106 is therefore differentiated by the digital signal differentiator 10 (made up of an adder 13 and a delay element 14), and the result is added to the output signal Q1 from the main loop 100, by the adder 12. As a result, the Vq1 term in equation (1) above is cancelled out, so that the overall relationship between the input digital signal X and the output digital signal Y of the circuit is expressed by the following equation: EQU Y=X+(1-z.sup.-1).sup.3 .multidot.Vq2 (4)
Such a circuit provides stable operation, irrespective of the fact that the quantization resolution of the sub-loop 106 is low, i.e. the output signal from that sub-loop can take only the two values +0.5. The reasons for that stability are as follows. The output value produced from the integrator 108, after being multiplied by the factor "a" in the factor multiplier 130, is fed back through the adder 128 to the local quantizer 103. Thus, when the output value from the integrator 108 is large, the input value that is supplied to the local quantizer 103 will also be large, and hence the resultant output value that is produced from the subtractor 2 will be a large negative value. That large negative value is applied through the subtractor 107 to the integrator 108, while the other input of the subtractor 107 is at a value whose maximum possible value is 0.5. Thus the subtractor 107 supplies a large negative value to the integrator 108, and hence the output from the integrator 108 will gradually become smaller.
In this way, since feedback is applied to the main loop 100 in a direction such as to reduce the magnitude of the output value from the integrator 108, the output from the 110 is restricted to at a small range of values, so that the quantization resolution of the local quantizer 111 can be made low. In this way, the values of the output signal Q1 from the main loop 100 can be established as -2, -1, . . . +2, i.e. a total of five values, while the values of the output signal Q2 from the sub-loop 106 can be established as -0.5 and +0.5, i.e. a total of two values. Hence, the output values of the output signal Y from the overall noise shaping requantizing circuit are -3, -2, . . . +3, i.e. a total of 7 values. Thus the input digital signal has been compressed to a range of 7 possible values, which can be expressed by 3 bits. Furthermore, equation (4) expresses the fact that the quantization error in the low frequency range has been moved to a high frequency range. Thus, the configuration shown in FIG. 18 provides the desired noise shaping operation, together with a compression of the number of bits required to represent the digital signal, and with no reduction of the dynamic range. When used with 64-times oversampling, for example, such a circuit provides a dynamic range of approximately 118 dB.
However with such a prior art noise shaping requantizing circuit, each time that a new output value begins to be produced from the integrator 108 in the sub-loop 106, signal operations are then again executed along a path which is, successively, from the output of the integrator 108-factor multiplier 130-adder 128-local quantizer 103-subtractor 2-subtractor 107-subtractor 109-integrator 110-local quantizer 111. Thus, high-speed operation is not achievable with such a configuration, i.e. there is a relatively long internal processing time for the feedback that is applied from the output of the integrator 108. In addition, the feedback is applied only from the output of the first stage integrator 108, and no feedback is applied from the next stage integrator, i.e. the integrator 110. Hence, this amounts to a condition in which no measures are taken to prevent oscillation or overflow from occurring for the integrator 110. Such problems are especially severe when the input digital signal is at a high level, and so result in a reduction of the dyamic range that can be achieved. Due to such problems of instability or overflow, it becomes difficult to use a sub-loop which has a third order (or higher order) noise shaping coefficent.
Specifically, when the level of the input signal X of the circuit is at a high value such as 0 dB (i.e. when the input signal level is close to 32768), the feedback that is applied by the factor multiplier 130 and the adder 128 becomes less effective. As a result, the noise level of the output signal is increased, and harmonic distortion is produced. With the circuit of FIG. 18, this results in a deterioration of approximately 25 dB in the noise level. To prevent that, it is necessary to limit the maximum amplitude of the input signal X to be less than 0 dB, and hence the dynamic range is reduced.